Command Line Tool

This chapter contains the auto-generated documentation of the command line interface for dumpling. The information you find here is a identical to the info found in the CLI command help pages.

dumpling

Generate ASIC tester vectors for PULP chips.

dumpling [OPTIONS] COMMAND [ARGS]...

install-completions

Install the command line tool’s bash completion for your shell

If you don’t provide any additional arguments this command tries to detect your current shell in use and appends the relevant settings to your .bashrc, .zshrc etc.

dumpling install-completions [OPTIONS] [[bash|fish|zsh|powershell]] [PATH]

Options

--append, --overwrite: Append the completion code to the file

-i, --case-insensitive, --no-case-insensitive: Case insensitive completion

Arguments

SHELL: Optional argument

PATH: Optional argument

rosetta

Generate stimuli for the TSMC65 Rosetta chip.

dumpling rosetta [OPTIONS] COMMAND [ARGS]...

Options

-p, --port-name <port_name>

Default:: jtag_and_reset_port

-w, --wtb-name <wtb_name>

Default:: multiport_ext_clk_wvtbl

-o, --output <output>

Default:: vectors.avc

-d, --device_cycle_name <device_cycle_name>

change-freq

Generate vectors to change the multiplication factor (MULT) and various other settings of the internal FLLs .

The FLL argument determines which of the two independent FLLs in Rosetta is configured.

The output frequency of the FLL is freq =<ref_freq>*<MULT>/<clk-div>.

Since we need to write to two registers, we have to wait long enough for the FLL to become stable again before we try to modify the second registers.

dumpling rosetta change-freq [OPTIONS] {PER_FLL|SOC_FLL} MULT

Options

--clk-div <clk_div>

Change the clock division factor of DCO clock to FLL output clock.

Options:: 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 | 256

-l, --lock

Gate the output clock with the FLL lock signal

Default:: False

--tolerance <tolerance>

The margin around the target multiplication factor for clock to be considered stable.

Default:: 512

--stable-cycles <stable_cycles>

The number of stable cycles unil LOCK is asserted.

Default:: 16

--unstable-cycles <unstable_cycles>

The number of unstable cycles unil LOCK is de-asserted.

Default:: 16

--enable-dithering

Enable dithering for higher frequency resolution.

Default:: False

--loop-gain-exponent <loop_gain_exponent>

The gain exponent of the feedback loop. Gain = 2^<value>

Default:: -7

-w, --wait-cycles <wait_cycles>

The number of jtag cycles to wait between writing the two FLL config registers.

Default:: 200

Arguments

FLL: Required argument

MULT: Required argument

check-eoc

Generate vectors to check for the end of computation.

Programs compiled with the pulp-sdk or pulp-runtime write their exit code to a special end-of-computation register in APB SOC Control when they leave main. The expected return code (by default 0) can be modified to assume any value between 0 and 255.

dumpling rosetta check-eoc [OPTIONS]

Options

--return-code <return_code>

The expected return code.

Default:: 0

-w, --wait-cycles <wait_cycles>

The number of cycles to wait for the eoc_register read operation to complete.

Default:: 10

execute-elf

Generate vectors to load and execute the given elf binary.

The command parses the binary supplied with the ‘–elf’ parameter and writes the generated stimuli to the given OUTPUT file. Additionally to the AVC ASCII output, a .wtb and .tmf with identical basename is created. The vectors take care of resetting the chip, halting the core, preloading the binary into L2 memory with optional verification and resuming the core. If an expected return code is supplied with the optional ‘–return-code’ flag, either a matched loop (polling) check or a single check (after a configurable number of idle clock cycles) for end of computation is added to the end of the stimuli vectors depending on the value of –eoc-wait-cycles.

dumpling rosetta execute-elf [OPTIONS]

Options

-e, --elf <elf>: Required The path to the elf binary to preload.

-r, --return-code <return_code>: Set a return code to check against during end of computation detection. A matched loop will be inserted to achieve

-w, --eoc-wait-cycles <eoc_wait_cycles>: If set to a non zero integer, wait the given number of cycles for end of computation check and bdon’t use

--verify, --no-verify

Enables/Disables verifying the content written to L2.

Default:: True

--blade, --no-blade

Enables/Disables the BLADE SRAM macros in Rosetta

Default:: True

--edram, --no-edram

Enables/Disables the eDRAM macros in Rosetta

Default:: True

--hd-mem-backend <hd_mem_backend>

Switches between SCM and eDRAM as the memory backend for the HD-Computing Accelerator

Default:: scm
Options:: edram | scm

--bypass-soc-fll: Bypass the FLL for the SoC clock and use the external SoC clock instead.

--bypass-per-fll: Bypass the FLL for the Peripheral clock and use the external clock instead.

-c, --compress

Compress all vectors by merging subsequent identical vectors into a single vector with increased repeat value.

Default:: False

--no-reset

Don’t reset the chip before executing the binary. Helpfull for debugging and to keep custom config preloaded via JTAG.

Default:: False

halt-core-verify-pc

Halt the core, optionally reading the program counter and resuming the core.

This command is mainly useful to verify or debug the execution state of a program. The generated vectors will halt the core, optionally read the programm counter and optionally resume the core.

E.g.:: dumpling rosetta -o halt_core.avc halt_core_verify_pc –pc 0c1c008080 –resume

Will halt the core, comparing the programm counter to the value 0x1c008080 and resuming the core afterwards.

The –assert-reset flag allows to keep the reset line asserted during the exeuction of core halt procedure. This allows to halt the core before it statrts to execute random data right after reset.

dumpling rosetta halt-core-verify-pc [OPTIONS]

Options

--pc <pc>: Read programm counter and compare it with the expected value provided

--resume, --no-resume

Resume the core after reading the program counter.

Default:: False

--assert-reset

Assert the chip reset line for the whole duration of the generated vectors.

Default:: False

-w, --wait-cycles <wait_cycles>

The number of cycles to wait before verifying that core was actually halted.

Default:: 10

reset-chip

Generate vectors to reset the core and the jtag interface

dumpling rosetta reset-chip [OPTIONS]

Options

-r, --reset-cycles <reset_cycles>

The number of cycles to assert the chip reset line.

Default:: 10

resume-core

Generate vectors to resume the core.

The vectors will instruct the RISC-V debug module via JTAG to resume the core and after a configurable number of JTAG clock cycles will verify that the core is in the ‘running’ state.

dumpling rosetta resume-core [OPTIONS]

Options

-w, --wait-cycles <wait_cycles>

The number of cycles to wait before verifying that core was actually resumed.

Default:: 10

verify-mem

Perform read transactions on the system bus and compare the values with expected ones

Each value of ADDRESS_VALUE_MAPPING should be of the kind ‘address=value[#Comment]’ where address and value are 32-bit value in hex notation and comment is an optional comment to attach to the vectors. E.g.:

write_mem “0x1c008080=0xdeadbeef#Write to start address” 0x1c008084=0x12345678

dumpling rosetta verify-mem [OPTIONS] [ADDRESS_VALUE_MAPPINGS]...

Options

--loop, --no-loop: If true, all matched loops in the verification vectors are replaced with reasonable delays to avoid the usage of matched loops altogether.

-c, --compress

Compress all vectors by merging subsequent identical vectors into a single vector with increased repeat value.

Default:: False

--use-pulp-tap

Use the PULP TAP for readout instead of the RISC-V Debug module.

Default:: False

--wait-cycles <wait_cycles>

The number of cycles to wait for the read operation to complete.

Default:: 10

Arguments

ADDRESS_VALUE_MAPPINGS: Optional argument(s)

verify-soc-config

Verify that the flags within the current value of the soc config register has the given values

dumpling rosetta verify-soc-config [OPTIONS]

Options

--blade, --no-blade

Enables/Disables the BLADE SRAM macros in Rosetta

Default:: True

--edram, --no-edram

Enables/Disables the eDRAM macros in Rosetta

Default:: True

--hd-mem-backend <hd_mem_backend>

Switches between SCM and eDRAM as the memory backend for the HD-Computing Accelerator

Default:: scm
Options:: edram | scm

--bypass-soc-fll: Bypass the FLL for the SoC clock and use the external SoC clock instead.

--bypass-per-fll: Bypass the FLL for the Peripheral clock and use the external clock instead.

write-mem

Perform write transactions to the system bus.

Each value of ADDRESS_VALUE_MAPPING should be of the kind ‘address=value[#Comment]’ where address and value are 32-bit value in hex notation and comment is an optional comment to attach to the vectors. E.g.:

write_mem “0x1c008080=0xdeadbeef#Write to start address” 0x1c008084=0x12345678

If the optional verify flag is provided, the data written will be read back for verification.

dumpling rosetta write-mem [OPTIONS] [ADDRESS_VALUE_MAPPINGS]...

Options

--verify, --no-verify

Enables/Disables verifying the content written to L2.

Default:: True

--loop, --no-loop: If true, all matched loops in the verification vectors are replaced with reasonable delays to avoid the usage of matched loops altogether.

-c, --compress

Compress all vectors by merging subsequent identical vectors into a single vector with increased repeat value.

Default:: False

Arguments

ADDRESS_VALUE_MAPPINGS: Optional argument(s)

write-soc-config

Writes the given static configuration value to the apb_soc_ctrl register.

dumpling rosetta write-soc-config [OPTIONS]

Options

--blade, --no-blade

Enables/Disables the BLADE SRAM macros in Rosetta

Default:: True

--edram, --no-edram

Enables/Disables the eDRAM macros in Rosetta

Default:: True

--hd-mem-backend <hd_mem_backend>

Switches between SCM and eDRAM as the memory backend for the HD-Computing Accelerator

Default:: scm
Options:: edram | scm

--bypass-soc-fll: Bypass the FLL for the SoC clock and use the external SoC clock instead.

--bypass-per-fll: Bypass the FLL for the Peripheral clock and use the external clock instead.

siracusa

Generate stimuli for the GF22 vega chip.

dumpling siracusa [OPTIONS] COMMAND [ARGS]...

Options

-p, --port-name <port_name>

Default:: jtag_and_reset_port

-w, --wtb-name <wtb_name>

Default:: multiport

-o, --output <output>

Default:: vectors.avc

-d, --device_cycle_name <device_cycle_name>

change-freq

Generate vectors to change the multiplication factor (MULT) and various other settings of the internal FLLs .

The FLL argument determines which of the three independent FLLs in Vega is configured. Which clock (soc_clk, per_clk and cluster_clk) is derived from which FLL depends on the clock selection settings in the APB_SOC_CONTROL module. By default, vega starts up using FLL1 for both, peripheral- (with some clk divider) and soc-clock and FLL2 for the cluster clock.

The output frequency of the FLL is freq =<ref_freq>*<MULT>/<clk-div>.

Since we need to write to two registers, we have to wait long enough for the FLL to become stable again before we try to modify the second registers.

dumpling siracusa change-freq [OPTIONS] {PLL1_SOC|PLL2_PER|PLL3_CLUSTER} MULT

Options

--enable, --disable

Enable/Disable the PLL altogether. If disabled, the other options have no effect but are still programmed into the PLL

Default:: True

--clk-div <clk_div>: Change the clock division factor of DCO clock to PLL output clock.

-l, --lock

Gate the output clock with the PLL lock signal

Default:: False

--lock-count <lock_count>

The number of stable cycles unil LOCK is asserted.

Default:: 16
Options:: 8 | 16 | 32 | 64

--vco-div, --no-vco-div

Enable/Disable the fixed divide-by-2 VCO clock divider.

Default:: True

--failsafe_en, --no-failsafe_en

Enable/Disable the failsafe feature within the PLL.

Default:: True

--freq_change_mask_count <freq_change_mask_count>

The number of cycles to mask the output clock during frequency changes.

Default:: 32

-w, --wait-cycles <wait_cycles>

The number of jtag cycles to wait between writing the PLL config registers.

Default:: 200

Arguments

PLL: Required argument

MULT: Required argument

check-eoc

Generate vectors to check for the end of computation.

Programs compiled with the pulp-sdk or pulp-runtime write their exit code to a special end-of-computation register in APB SOC Control when they leave main. The expected return code (by default 0) can be modified to assume any value between 0 and 255.

dumpling siracusa check-eoc [OPTIONS]

Options

--return-code <return_code>

The expected return code.

Default:: 0

-w, --wait-cycles <wait_cycles>

The number of cycles to wait for the eoc_register read operation to complete.

Default:: 10

configure-gpio

Configure the provided GPIO to expose the desired function.

dumpling siracusa configure-gpio [OPTIONS] {port_gpio_gpio00|port_i2c0_scl|por
                                 t_i2c0_sda|port_i3c0_puc|port_i3c0_scl|port_i
                                 3c0_sda|port_i3c1_puc|port_i3c1_scl|port_i3c1
                                 _sda|port_qspim0_csn0|port_qspim0_csn1|port_q
                                 spim0_csn2|port_qspim0_csn3|port_qspim0_sck|p
                                 ort_qspim0_sdio0|port_qspim0_sdio1|port_qspim
                                 0_sdio2|port_qspim0_sdio3|port_qspis0_csn|por
                                 t_qspis0_sck|port_qspis0_sdio0|port_qspis0_sd
                                 io1|port_qspis0_sdio2|port_qspis0_sdio3|port_
                                 uart0_rx|port_uart0_tx|register} GPIO_NR

Arguments

FUNCTION: Required argument

GPIO_NR: Required argument

execute-elf

Generate vectors to load and execute the given elf binary.

The command parses the binary supplied with the ‘–elf’ parameter and writes the generated stimuli to the given OUTPUT file. Additionally to the AVC ASCII output, a .wtb and .tmf with identical basename is created. The vectors take care of resetting the chip, halting the core, preloading the binary into L2 memory with optional verification and resuming the core. If an expected return code is supplied with the optional ‘–return-code’ flag, either a matched loop (polling) check or a single check (after a configurable number of idle clock cycles) for end of computation is added to the end of the stimuli vectors depending on the value of –eoc-wait-cycles.

dumpling siracusa execute-elf [OPTIONS]

Options

-e, --elf <elf>: Required The path to the elf binary to preload.

-r, --return-code <return_code>: Set a return code to check against during end of computation detection. A matched loop will be inserted to achieve

-w, --eoc-wait-cycles <eoc_wait_cycles>: If set to a non zero integer, wait the given number of cycles for end of computation check and bdon’t use

--verify, --no-verify

Enables/Disables verifying the content written to L2.

Default:: True

-c, --compress

Compress all vectors by merging subsequent identical vectors into a single vector with increased repeat value.

Default:: False

--no-reset

Don’t reset the chip before executing the binary. Helpfull for debugging and to keep custom config preloaded via JTAG.

Default:: False

halt-core-verify-pc

Halt the core, optionally reading the program counter and resuming the core.

This command is mainly useful to verify or debug the execution state of a program. The generated vectors will halt the core, optionally read the programm counter and optionally resume the core.

E.g.:: dumpling vega -o halt_core.avc halt_core_verify_pc –pc 0c1c008080 –resume

Will halt the core, comparing the programm counter to the value 0x1c008080 and resuming the core afterwards.

The –assert-reset flag allows to keep the reset line asserted during the exeuction of core halt procedure. This allows to halt the core before it statrts to execute random data right after reset.

dumpling siracusa halt-core-verify-pc [OPTIONS]

Options

--pc <pc>: Read programm counter and compare it with the expected value provided

--resume, --no-resume

Resume the core after reading the program counter.

Default:: False

--assert-reset

Assert the chip reset line for the whole duration of the generated vectors.

Default:: False

-w, --wait-cycles <wait_cycles>

The number of cycles to wait before verifying that core was actually halted.

Default:: 10

reset-chip

Generate vectors to reset the core and the jtag interface

dumpling siracusa reset-chip [OPTIONS]

Options

-r, --reset-cycles <reset_cycles>

The number of cycles to assert the chip reset line.

Default:: 10

resume-core

Generate vectors to resume the core.

The vectors will instruct the RISC-V debug module via JTAG to resume the core and after a configurable number of JTAG clock cycles will verify that the core is in the ‘running’ state.

dumpling siracusa resume-core [OPTIONS]

Options

-w, --wait-cycles <wait_cycles>

The number of cycles to wait before verifying that core was actually resumed.

Default:: 10

verify-idcode

Generate vectors to verify IDCODE of the RISC-V debug unit.

Puts all taps except the debug unit into bypass mode and verifies the value of the debug units IDCODE register. In Siracusa, the value should match “0x249511C3”. After the idcode read-out, the debug unit TAP remains selected.

dumpling siracusa verify-idcode [OPTIONS]

verify-mem

Perform read transactions on the system bus and compare the values with expected ones

Each value of ADDRESS_VALUE_MAPPING should be of the kind ‘address=value[#Comment]’ where address and value are 32-bit value in hex notation and comment is an optional comment to attach to the vectors. E.g.:

verify_mem “0x1c008080=0xdeadbeef#Expecting to read 0xdeadbeef from start address” 0x1c008084=0x12345678

dumpling siracusa verify-mem [OPTIONS] [ADDRESS_VALUE_MAPPINGS]...

Options

--loop, --no-loop: If true, all matched loops in the verification vectors are replaced with reasonable delays to avoid the usage of matched loops altogether.

-c, --compress

Compress all vectors by merging subsequent identical vectors into a single vector with increased repeat value.

Default:: False

--use-pulp-tap

Use the PULP TAP for readout instead of the RISC-V Debug module.

Default:: False

--wait-cycles <wait_cycles>

The number of cycles to wait for the read operation to complete. Only relevant when pulp-tap is used

Default:: 10

Arguments

ADDRESS_VALUE_MAPPINGS: Optional argument(s)

write-mem

Perform write transactions to the system bus.

Each value of ADDRESS_VALUE_MAPPING should be of the kind ‘address=value[#Comment]’ where address and value are 32-bit value in hex notation and comment is an optional comment to attach to the vectors. E.g.:

write_mem “0x1c008080=0xdeafbeef#Write to start address” 0x1c008084=0x12345678

If the optional verify flag is provided, the data written will be read back for verification.

dumpling siracusa write-mem [OPTIONS] [ADDRESS_VALUE_MAPPINGS]...

Options

--verify, --no-verify

Enables/Disables verifying the content written to L2.

Default:: True

--loop, --no-loop: If true, all matched loops in the verification vectors are replaced with reasonable delays to avoid the usage of matched loops altogether.

-c, --compress

Compress all vectors by merging subsequent identical vectors into a single vector with increased repeat value.

Default:: False

Arguments

ADDRESS_VALUE_MAPPINGS: Optional argument(s)

vega

Generate stimuli for the GF22 vega chip.

dumpling vega [OPTIONS] COMMAND [ARGS]...

Options

-p, --port-name <port_name>

Default:: jtag_and_reset_port

-w, --wtb-name <wtb_name>

Default:: multiport

-o, --output <output>

Default:: vectors.avc

-d, --device_cycle_name <device_cycle_name>

change-freq

Generate vectors to change the multiplication factor (MULT) and various other settings of the internal FLLs .

The FLL argument determines which of the three independent FLLs in Vega is configured. Which clock (soc_clk, per_clk and cluster_clk) is derived from which FLL depends on the clock selection settings in the APB_SOC_CONTROL module. By default, vega starts up using FLL1 for both, peripheral- (with some clk divider) and soc-clock and FLL2 for the cluster clock.

The output frequency of the FLL is freq =<ref_freq>*<MULT>/<clk-div>.

Since we need to write to two registers, we have to wait long enough for the FLL to become stable again before we try to modify the second registers.

dumpling vega change-freq [OPTIONS] {FLL1|FLL2|FLL3} MULT

Options

--clk-div <clk_div>

Change the clock division factor of DCO clock to FLL output clock.

Options:: 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 | 256

-l, --lock

Gate the output clock with the FLL lock signal

Default:: False

--tolerance <tolerance>

The margin around the target multiplication factor for clock to be considered stable.

Default:: 512

--stable-cycles <stable_cycles>

The number of stable cycles unil LOCK is asserted.

Default:: 16

--unstable-cycles <unstable_cycles>

The number of unstable cycles unil LOCK is de-asserted.

Default:: 16

--enable-dithering

Enable dithering for higher frequency resolution.

Default:: False

--loop-gain-exponent <loop_gain_exponent>

The gain exponent of the feedback loop. Gain = 2^<value>

Default:: -7

-w, --wait-cycles <wait_cycles>

The number of jtag cycles to wait between writing the two FLL config registers.

Default:: 200

Arguments

FLL: Required argument

MULT: Required argument

check-eoc

Generate vectors to check for the end of computation.

Programs compiled with the pulp-sdk or pulp-runtime write their exit code to a special end-of-computation register in APB SOC Control when they leave main. The expected return code (by default 0) can be modified to assume any value between 0 and 255.

dumpling vega check-eoc [OPTIONS]

Options

--return-code <return_code>

The expected return code.

Default:: 0

-w, --wait-cycles <wait_cycles>

The number of cycles to wait for the eoc_register read operation to complete.

Default:: 10

disable-observability

Disable the internal signal observability feature.

This command generates vectors that restore the default operation mode of the PWM3 pad and disable the observability of internal signals.

dumpling vega disable-observability [OPTIONS]

enable-observability

Generate vectors to enable observability SIGNAL on the PWM3 pad.

This command enables the observability feature for a selection of important internal signals of the chip and routes them to the PWM3 pad. Use the disable_observability command to generate vectors that restore the PWM3 pad’s default mode of operation.

dumpling vega enable-observability [OPTIONS] {pmu_soc_trc_clk_o|pmu_soc_rst_re
                                   t_n_o|pmu_soc_rst_control_o|pmu_soc_rst_con
                                   trol_ack_i|pmu_soc_clken_o|pmu_soc_trc_ret_
                                   n_o|pmu_soc_trc_pok_ret_i|pmu_cluster_trc_r
                                   et_n_o|pmu_cluster_trc_pok_ret_i|pmu_csi2_t
                                   rc_ext_n_o|pmu_csi2_trc_pok_ext_i|pmu_emram
                                   _core_trc_ext_n_o|pmu_emram_core_trc_pok_ex
                                   t_i|pmu_smartwake_trc_ext_n_o|pmu_smartwake
                                   _trc_pok_ext_i|ref_clk_i|por_n_i|io_ls_avd_
                                   ok_o|io_ls_pok_i|io_hs_avd_ok_o|io_hs_pok_i
                                   |emram_io_avd_ok_o|emram_io_pok_i|safe_rar_
                                   rok_i|safe_rar_vsel_strobe_o|safe_rar_vsel_
                                   reg_o|logic_rar_rok_i|logic_rar_vsel_strobe
                                   _o|vref_06_en_o|vref_12_en_o|vref_06_ok_i|v
                                   ref_12_ok_i}

Arguments

SIGNAL: Required argument

execute-elf

Generate vectors to load and execute the given elf binary.

The command parses the binary supplied with the ‘–elf’ parameter and writes the generated stimuli to the given OUTPUT file. Additionally to the AVC ASCII output, a .wtb and .tmf with identical basename is created. The vectors take care of resetting the chip, halting the core, preloading the binary into L2 memory with optional verification and resuming the core. If an expected return code is supplied with the optional ‘–return-code’ flag, either a matched loop (polling) check or a single check (after a configurable number of idle clock cycles) for end of computation is added to the end of the stimuli vectors depending on the value of –eoc-wait-cycles.

dumpling vega execute-elf [OPTIONS]

Options

-e, --elf <elf>: Required The path to the elf binary to preload.

-r, --return-code <return_code>: Set a return code to check against during end of computation detection. A matched loop will be inserted to achieve

-w, --eoc-wait-cycles <eoc_wait_cycles>: If set to a non zero integer, wait the given number of cycles for end of computation check and bdon’t use

--verify, --no-verify

Enables/Disables verifying the content written to L2.

Default:: True

-c, --compress

Compress all vectors by merging subsequent identical vectors into a single vector with increased repeat value.

Default:: False

--no-reset

Don’t reset the chip before executing the binary. Helpfull for debugging and to keep custom config preloaded via JTAG.

Default:: False

halt-core-verify-pc

Halt the core, optionally reading the program counter and resuming the core.

This command is mainly useful to verify or debug the execution state of a program. The generated vectors will halt the core, optionally read the programm counter and optionally resume the core.

E.g.:: dumpling vega -o halt_core.avc halt_core_verify_pc –pc 0c1c008080 –resume

Will halt the core, comparing the programm counter to the value 0x1c008080 and resuming the core afterwards.

The –assert-reset flag allows to keep the reset line asserted during the exeuction of core halt procedure. This allows to halt the core before it statrts to execute random data right after reset.

dumpling vega halt-core-verify-pc [OPTIONS]

Options

--pc <pc>: Read programm counter and compare it with the expected value provided

--resume, --no-resume

Resume the core after reading the program counter.

Default:: False

--assert-reset

Assert the chip reset line for the whole duration of the generated vectors.

Default:: False

-w, --wait-cycles <wait_cycles>

The number of cycles to wait before verifying that core was actually halted.

Default:: 10

reset-chip

Generate vectors to reset the core and the jtag interface

dumpling vega reset-chip [OPTIONS]

Options

-r, --reset-cycles <reset_cycles>

The number of cycles to assert the chip reset line.

Default:: 10

resume-core

Generate vectors to resume the core.

The vectors will instruct the RISC-V debug module via JTAG to resume the core and after a configurable number of JTAG clock cycles will verify that the core is in the ‘running’ state.

dumpling vega resume-core [OPTIONS]

Options

-w, --wait-cycles <wait_cycles>

The number of cycles to wait before verifying that core was actually resumed.

Default:: 10

set-clk-bypass

Set the internal clock bypass register to bypass reference clock or FLL clock

dumpling vega set-clk-bypass [OPTIONS]

Options

--qosc_bypass: Bypass the crystall oscilator

--ref_bypass: Bypass the reference clock

--per_fll_bypass: Bypass peripheral fll

--soc_fll_bypass: Bypass SoC fll

--cluster_fll_bypass: Bypass Cluster fll

verify-mem

Perform read transactions on the system bus and compare the values with expected ones

Each value of ADDRESS_VALUE_MAPPING should be of the kind ‘address=value[#Comment]’ where address and value are 32-bit value in hex notation and comment is an optional comment to attach to the vectors. E.g.:

write_mem “0x1c008080=0xdeadbeef#Write to start address” 0x1c008084=0x12345678

dumpling vega verify-mem [OPTIONS] [ADDRESS_VALUE_MAPPINGS]...

Options

--loop, --no-loop: If true, all matched loops in the verification vectors are replaced with reasonable delays to avoid the usage of matched loops altogether.

-c, --compress

Compress all vectors by merging subsequent identical vectors into a single vector with increased repeat value.

Default:: False

--use-pulp-tap

Use the PULP TAP for readout instead of the RISC-V Debug module.

Default:: False

--wait-cycles <wait_cycles>

The number of cycles to wait for the read operation to complete. Only relevant when pulp-tap is used

Default:: 10

Arguments

ADDRESS_VALUE_MAPPINGS: Optional argument(s)

write-mem

Perform write transactions to the system bus.

Each value of ADDRESS_VALUE_MAPPING should be of the kind ‘address=value[#Comment]’ where address and value are 32-bit value in hex notation and comment is an optional comment to attach to the vectors. E.g.:

write_mem “0x1c008080=0xdeafbeef#Write to start address” 0x1c008084=0x12345678

If the optional verify flag is provided, the data written will be read back for verification.

dumpling vega write-mem [OPTIONS] [ADDRESS_VALUE_MAPPINGS]...

Options

--verify, --no-verify

Enables/Disables verifying the content written to L2.

Default:: True

--loop, --no-loop: If true, all matched loops in the verification vectors are replaced with reasonable delays to avoid the usage of matched loops altogether.

-c, --compress

Compress all vectors by merging subsequent identical vectors into a single vector with increased repeat value.

Default:: False

Arguments

ADDRESS_VALUE_MAPPINGS: Optional argument(s)