dumpling.JTAGTaps package

Submodules

dumpling.JTAGTaps.JTAGTap module

class dumpling.JTAGTaps.JTAGTap.JTAGRegister(name, IR_value, DR_size, default_value: Optional[str] = None)[source]

Bases: object

A convenience class used by class JTAGTap to instantiate JTAG Registers.

Parameters:

  • name (str) – The human readable name of the JTAG Tap (e.g. “IDCODE”).

  • IR_value (str) – The value that must be written to the IR to select this JTAG Register has a binary string (

  • "0100111") (e.g.) –

  • number. (default) –

atach(tap: JTAGTap)[source]
read(reg_length=None, expected_value: Optional[str] = None, comment='')[source]

A convenience function to generate vectors to read from a JTAG register using dot notation (e.g. my_tap.reg1.read().

The stimuli generated will first select the correct IR and put all other TAPs into bypass. Then it will shift DR the data out of chip.

Internally, the register will forward the call to the JTAG driver.

This function will fail if the JTAGRegister has not yet been attached to a JTAG Tap!

Parameters:

  • reg_length (int) – The number of bits to read. If none, the DR length attribute of the register itself will be used.

  • expected_value (str) – A string (hex or binary notation) of a value to compare to the data register. If none, the value will not be compared (‘X’)

  • comment (str) – An optional comment with which to annotate the generated vectors

Returns:

A list of vectors

Return type:

List[Mapping]

class dumpling.JTAGTaps.JTAGTap.JTAGTap(name, IR_size, driver: JTAGDriver)[source]

Bases: object

Create a JTAGTap config object with a user defineable name and the given IR register size in bits.

The constructor will automatically add the BYPASS register to the JTAGTap object using the IR_size to determine the BYPASS register’s IR value.

Create subclasses of this class that implement tap specific functions. That ‘driver’ field contains a handle to the jtag_driver and allows interaction with jtag chain.

Parameters:

  • name (str) – The human readable name of this TAP

  • IR_size (int) – The IR size of this TAP in bits

  • driver ('JTAGDriver') –

dumpling.JTAGTaps.PulpJTAGTap module

class dumpling.JTAGTaps.PulpJTAGTap.PULPJtagTap(driver: JTAGDriver)[source]

Bases: JTAGTap

See also

Check the adv_dbg documentation for details on the protocol used for this JTAGTap

DBG_MODULE_ID = BitArray('0b100000')
class DBG_OP(value)[source]

Bases: Enum

An enumeration.

INT_REG_SELECT = '0xD'
INT_REG_WRITE = '0x9'
NOP = '0x0'
READ16 = '0x6'
READ32 = '0x7'
READ64 = '0x8'
READ8 = '0x5'
WRITE16 = '0x2'
WRITE32 = '0x3'
WRITE64 = '0x4'
WRITE8 = '0x1'
to_bits()[source]
init_pulp_tap()[source]
loadL2(elf_binary: str, comment='')[source]
module_select(comment='')[source]
read32(start_addr: BitArray, expected_data: List[BitArray], retries=1, comment='')[source]
read32_no_loop(start_addr: BitArray, expected_data: List[BitArray], wait_cycles=3, comment='')[source]
read_burst(expected_data: List[BitArray], comment='', retries=1)[source]
read_burst_no_loop(expected_data: List[BitArray], wait_cycles=3, comment='')[source]
set_config_reg(soc_jtag_reg_value: BitArray, sel_fll_clk: bool, comment='')[source]

Generates stimuli to program the config register.

Parameters:

  • soc_jtag_reg_value (BitArray) – An 8-bit value represented as a BitArray of length 8 with character 0,1

  • sel_fll_clk (bool) – True if the internal FLL should be used for clock generation, False if the external reference clock should be directly used for clock gen.

  • comment (str) – A string with which the first vector of the returned stimuli vectors will be annotated as a comment. If None, a default comment will be used.

Returns:

The generated vectors. The format of those vectors depends on the actual implementation of the VectorWriter instance used

setup_burst(cmd: DBG_OP, start_addr: BitArray, nwords: int, comment='')[source]
verifyL2(elf_binary: str, retries=1, comment='')[source]
verifyL2_no_loop(elf_binary: str, comment='')[source]
verify_config_reg(soc_jtag_reg_value: BitArray, sel_fll_clk: bool, comment='')[source]
write32(start_addr: BitArray, data: List[BitArray], comment='')[source]
write_burst(data: List[BitArray], comment='')[source]

dumpling.JTAGTaps.PulpJTAGTapRosetta module

class dumpling.JTAGTaps.PulpJTAGTapRosetta.PULPJTagTapRosetta(driver: JTAGDriver)[source]

Bases: PULPJtagTap

set_config_reg(soc_jtag_reg_value: BitArray, soc_fll_bypass_en: bool, per_fll_bypass_en: bool, blade_disable: bool, edram_disable: bool, hd_mem_backend_use_edram: bool)[source]

Generates stimuli to program the config register.

Parameters:

  • soc_jtag_reg_value (BitArray) – An 8-bit value represented as a BitArray of length 8 with character 0,1

  • sel_fll_clk (bool) – True if the internal FLL should be used for clock generation, False if the external reference clock should be directly used for clock gen.

  • comment (str) – A string with which the first vector of the returned stimuli vectors will be annotated as a comment. If None, a default comment will be used.

Returns:

The generated vectors. The format of those vectors depends on the actual implementation of the VectorWriter instance used

verify_config_reg(soc_jtag_reg_value: BitArray, soc_fll_bypass_en: bool, per_fll_bypass_en: bool, blade_disable: bool, edram_disable: bool, hd_mem_backend_use_edram: bool)[source]

dumpling.JTAGTaps.PulpJTAGTapVega module

class dumpling.JTAGTaps.PulpJTAGTapVega.PULPJtagTapVega(driver: JTAGDriver)[source]

Bases: JTAGTap

See also

Check the adv_dbg documentation for details on the protocol used for this JTAGTap

DBG_MODULE_ID = BitArray('0b100000')
class DBG_OP(value)[source]

Bases: Enum

An enumeration.

INT_REG_SELECT = '0xD'
INT_REG_WRITE = '0x9'
NOP = '0x0'
READ16 = '0x6'
READ32 = '0x7'
READ64 = '0x8'
READ8 = '0x5'
WRITE16 = '0x2'
WRITE32 = '0x3'
WRITE64 = '0x4'
WRITE8 = '0x1'
to_bits()[source]
class OBSERVABLE_SIGNAL(value)[source]

Bases: Enum

An enumeration.

emram_io_avd_ok_o = 21
emram_io_pok_i = 22
io_hs_avd_ok_o = 19
io_hs_pok_i = 20
io_ls_avd_ok_o = 17
io_ls_pok_i = 18
logic_rar_rok_i = 26
logic_rar_vsel_strobe_o = 27
pmu_cluster_trc_pok_ret_i = 8
pmu_cluster_trc_ret_n_o = 7
pmu_csi2_trc_ext_n_o = 9
pmu_csi2_trc_pok_ext_i = 10
pmu_emram_core_trc_ext_n_o = 11
pmu_emram_core_trc_pok_ext_i = 12
pmu_smartwake_trc_ext_n_o = 13
pmu_smartwake_trc_pok_ext_i = 14
pmu_soc_clken_o = 4
pmu_soc_rst_control_ack_i = 3
pmu_soc_rst_control_o = 2
pmu_soc_rst_ret_n_o = 1
pmu_soc_trc_clk_o = 0
pmu_soc_trc_pok_ret_i = 6
pmu_soc_trc_ret_n_o = 5
por_n_i = 16
ref_clk_i = 15
safe_rar_rok_i = 23
safe_rar_vsel_reg_o = 25
safe_rar_vsel_strobe_o = 24
vref_06_en_o = 28
vref_06_ok_i = 30
vref_12_en_o = 29
vref_12_ok_i = 31
disable_observability()[source]

Disable the observability functionality and make the PWM3 pad act normally again.

Returns: The vectors associated to the pad

enable_observability(signal: OBSERVABLE_SIGNAL, pulldown_enable=False, pullup_enable=False, drv_strength=0)[source]

Programs the observability register to generate make one 32 different internal signals available to the PWM3 pad

Parameters:

  • (OBSERVABLE_SIGNAL] (signal) – The signal for which to enable the observability

  • pulldown_enable (bool) – Whether to enable the pull-down resistor of the observability pad

  • pullup_enable (bool) – Whether to enable the pull-up resistor of the observability pad

  • drv_strength (int) – The driving strength to use for the register (value between 0-3 inclusive)

Returns:

The vectors corresponding to the operation

Return type:

List

init_pulp_tap()[source]
loadL2(elf_binary: str, comment='')[source]
module_select(comment='')[source]
read32(start_addr: BitArray, expected_data: List[BitArray], retries=1, comment='')[source]
read32_no_loop(start_addr: BitArray, expected_data: List[BitArray], wait_cycles=1, comment='')[source]
read_burst(expected_data: List[BitArray], comment='', retries=1)[source]
read_burst_no_loop(expected_data: List[BitArray], wait_cycles=1, comment='')[source]
set_clk_bypass_reg(qosc_byp: bool = False, ref_clk_byp: bool = False, per_fll_byp: bool = False, soc_fll_byp: bool = True, cluster_fll_byp: bool = True)[source]
setup_burst(cmd: DBG_OP, start_addr: BitArray, nwords: int, comment='')[source]
verifyL2(elf_binary: str, retries=1, comment='')[source]
verifyL2_no_loop(elf_binary: str, comment='')[source]
write32(start_addr: BitArray, data: List[BitArray], comment='')[source]
write_burst(data: List[BitArray], comment='')[source]

dumpling.JTAGTaps.RISCVDebugTap module

class dumpling.JTAGTaps.RISCVDebugTap.DMAbstractCmd(cmd_type: DMAbstractCmdType, reg: RISCVReg, write: bool = False, transfer: bool = False, postexec: bool = False, aarpostinc: bool = False, aarsize: int = 2)[source]

Bases: object

to_bits()[source]
class dumpling.JTAGTaps.RISCVDebugTap.DMAbstractCmdType(value)[source]

Bases: Enum

An enumeration.

ACCESS_MEM = 2
ACCESS_REG = 0
QUICK_ACCESS = 1
to_bits()[source]
class dumpling.JTAGTaps.RISCVDebugTap.DMIOp(value)[source]

Bases: Enum

An enumeration.

NOP = '00'
READ = '01'
WRITE = '10'
class dumpling.JTAGTaps.RISCVDebugTap.DMIResult(value)[source]

Bases: Enum

An enumeration.

OP_FAILED = '10'
OP_PENDING = '11'
OP_SUCCESS = '00'
class dumpling.JTAGTaps.RISCVDebugTap.DMRegAddress(value)[source]

Bases: Enum

An enumeration.

ABSTRACTAUTO = '0011000'
ABSTRACTCS = '0010110'
AUTHDATA = '0110000'
COMMAND = '0010111'
CONFSTRPTR0 = '0011001'
CONFSTRPTR1 = '0011010'
CONFSTRPTR2 = '0011011'
CONFSTRPTR3 = '0011100'
DATA11 = '0001111'
DATAO = '0000100'
DMCONTROL = '0010000'
DMSTATUS = '0010001'
HALTSUM0 = '1000000'
HALTSUM1 = '0010011'
HALTSUM2 = '0110100'
HALTSUM3 = '0110101'
HARTINFO = '0010010'
HAWINDOW = '0010101'
HAWINDOWSEL = '0010100'
NEXTDM = '0011101'
NO_REG = '0000000'
PROGBUF0 = '0100000'
PROGBUF15 = '0101111'
SBADDRESS0 = '0111001'
SBADDRESS1 = '0111010'
SBADDRESS2 = '0111011'
SBADDRESS3 = '0110111'
SBCS = '0111000'
SBDATA0 = '0111100'
SBDATA1 = '0111101'
SBDATA2 = '0111110'
SBDATA3 = '0111111'
class dumpling.JTAGTaps.RISCVDebugTap.RISCVDebugTap(driver: JTAGDriver, idcode: str = '0x249511C3')[source]

Bases: JTAGTap

check_end_of_computation(expected_return_code: int, wait_cycles=10, eoc_reg_addr='0x1a1040a0')[source]
dmi_hardreset()[source]
dmi_reset()[source]
enable_sbreadonaddr()[source]
halt_hart(hartsel: BitArray, comment='', retries=1)[source]
halt_hart_no_loop(hartsel: BitArray, comment='', wait_cycles=10)[source]
init_dmi()[source]
readMem(addr: BitArray, expected_data: BitArray, retries=1, comment='')[source]
readMem_no_loop(addr: BitArray, expected_data: BitArray, wait_cycles, comment='')[source]
read_debug_reg(dmi_addr: DMRegAddress, expected_data: str, retries=1, comment='')[source]
read_debug_reg_no_loop(dmi_addr: DMRegAddress, expected_data: str, wait_cycles=0, comment='')[source]
read_reg_abstract_cmd(reg: RISCVReg, expected_data, retries=1, comment='')[source]
read_reg_abstract_cmd_no_loop(reg: RISCVReg, expected_data, wait_cycles=10, comment='')[source]
resume_harts(hartsel: BitArray, comment='', retries=1)[source]
resume_harts_no_loop(hartsel: BitArray, comment='', wait_cycles=10)[source]
set_command(cmd: DMAbstractCmd, comment='', retries=1)[source]
set_command_no_loop(cmd: DMAbstractCmd, comment='', wait_cycles=10)[source]
set_dmactive(dmactive: bool)[source]
set_dmi(dm_op: DMIOp, dmi_addr: DMRegAddress, new_dm_data: str, expected_dm_status=None, expected_dm_data=None, comment='')[source]
verify_idcode()[source]

Selects the IDCODE register of this tap (all other TAPs are put into bypass mode) and verifies that IDCODE matches the expected value.

wait_command(retries=1, comment='')[source]
wait_for_end_of_computation(expected_return_code: int, idle_vector_count=10, max_retries=10, eoc_reg_addr='0x1a1040a0')[source]
writeMem(addr: BitArray, data: BitArray, verify_completion=True, retries=1, comment='')[source]
write_debug_reg(dmi_addr: DMRegAddress, data: str, verify_completion=True, retries=1, comment='')[source]
write_reg_abstract_cmd(reg: RISCVReg, data: BitArray, retries=1, comment='')[source]
write_reg_abstract_cmd_no_loop(reg: RISCVReg, data: BitArray, comment='')[source]
class dumpling.JTAGTaps.RISCVDebugTap.RISCVReg(value)[source]

Bases: Enum

An enumeration.

CSR_BRANCH_JUMP = '0xC0B'
CSR_CALL = '0xC0C'
CSR_CYCLE = '0xC00'
CSR_DCACHE = '0x701'
CSR_DCSR = '0x7b0'
CSR_DPC = '0x7b1'
CSR_DSCRATCH0 = '0x7b2'
CSR_DSCRATCH1 = '0x7b3'
CSR_DTLB_MISS = '0xC06'
CSR_EXCEPTION = '0xC09'
CSR_EXCEPTION_RET = '0xC0A'
CSR_FCSR = '0x003'
CSR_FFLAGS = '0x001'
CSR_FRM = '0x002'
CSR_FTRAN = '0x800'
CSR_ICACHE = '0x700'
CSR_IF_EMPTY = '0xC10'
CSR_INSTRET = '0xC02'
CSR_ITLB_MISS = '0xC05'
CSR_L1_DCACHE_MISS = '0xC04'
CSR_L1_ICACHE_MISS = '0xC03'
CSR_LOAD = '0xC07'
CSR_MARCHID = '0xF12'
CSR_MCAUSE = '0x342'
CSR_MCOUNTEREN = '0x306'
CSR_MCYCLE = '0xB00'
CSR_MEDELEG = '0x302'
CSR_MEPC = '0x341'
CSR_MHARTID = '0xF14'
CSR_MIDELEG = '0x303'
CSR_MIE = '0x304'
CSR_MIMPID = '0xF13'
CSR_MINSTRET = '0xB02'
CSR_MIP = '0x344'
CSR_MISA = '0x301'
CSR_MIS_PREDICT = '0xC0E'
CSR_MSCRATCH = '0x340'
CSR_MSTATUS = '0x300'
CSR_MTVAL = '0x343'
CSR_MTVEC = '0x305'
CSR_MVENDORID = '0xF11'
CSR_PMPADDR0 = '0x3B0'
CSR_PMPCFG0 = '0x3A0'
CSR_RET = '0xC0D'
CSR_SATP = '0x180'
CSR_SB_FULL = '0xC0F'
CSR_SCAUSE = '0x142'
CSR_SCOUNTEREN = '0x106'
CSR_SEPC = '0x141'
CSR_SIE = '0x104'
CSR_SIP = '0x144'
CSR_SSCRATCH = '0x140'
CSR_SSTATUS = '0x100'
CSR_STORE = '0xC08'
CSR_STVAL = '0x143'
CSR_STVEC = '0x105'
CSR_TDATA1 = '0x7A1'
CSR_TDATA2 = '0x7A2'
CSR_TDATA3 = '0x7A3'
CSR_TIME = '0xC01'
CSR_TINFO = '0x7A4'
CSR_TSELECT = '0x7A0'
to_bits()[source]

Module contents